USB Measurement Interface MI-1
The heart of the project
I originaly intended to use AK4493 DAC and AK5572 ADC. But as AK4493 went extinct I switched to AK4490. And still – I had to go through a lot of cancelled orders, refunds and other nonsense’s till I managed to get my hands on one of those chips.
I had to literally salvage them from these Chinese junk DAC’s. I didn’t measure any of these boards. If you ever tried to design and route a board for the modern multi-bit DAC – you know how much effort it takes to squeeze even the datasheet performance out of AKM parts. So just looking at these pathetic attempts here with shiny axial à la “Phillips boutique” capacitors (all fake of course) made me lough hard :). I guess this is all adequate for the price (these boards are 30-40$ a pop). On the other hand, paying 30$ for a chip that just a couple months ago was readily available everywhere for just over 6$ is kinda insane. But that’s current reality. There are no good alternatives for AKM parts if you only interested in THD performance game. Maybe ES9012/ES9018 could hold candle here, but ESS distribution model and lack of datasheets make them same risky unobtainium as AKM parts.
Datasheet distortion parameters of AK4490 DAC and AK5572 ADC.
Datasheets of both AKM parts suggests project SINAD target of -112dBFS. In above datasheets THD+N and SINAD (or S/(N+D)) are equal as measurement BW is almost Fs/2. I will be using this interface mainly for frequency spectrum analysis so my real benchmark is cleanest possible overall spectrum.
FFT spectrum of AK4490 and AK5554 evaluation boards.
FFT’s from eval. boards of AK4490 and AK5554 suggest I should aim for -110dB spuriuos free range (SFDR) for DAC and -120dB SFDR for ADC. There are no FFT’s for AKK5572 reference design, but AK5554 seems to be a close relative.
USB part design
XMOS devices have now become industry standard when it comes to UAC-2 audio. These are strange beasts, combining real-time parallel processing multi-controller capabilities with a high-speed advantages of FPGA/CPLD world. XS1-L6A-64-TQ48 or newer XU208-256-TQ64-C10 devices are used in almost all current USB audio interfaces.
But here is a “small” problem again… You can’t buy them anywhere. They are still in production, just nobody has any stock. Is this pandemic IC crisis related? Who knows… (XMOS does). But what a wonderful times we live in! IC hunger games anyone? Last man standing can meet the final boss and win a chance to compete for last available 45 pcs. of XS1-L8A-64-LQ64-C5. Splendid!
And there is a good reason why there is still a lot of LQ64 devices available (even when writing this) – they are a worst choice for USB2.0 reference design.
As can be seen from port-map above LQ64 package doesn’t have any free 32bit port pins available (all shared 32bit port pins are used for USB tile). Which means that despite a larger package and more pins – LQ64 has MUCH less I/O capabilities then a smaller TQ48 package.
For a simple 2ch in/out DAC/ADC design you can just get away by remapping only free 1bit ports P1J0 and P1K0 to do clock select and reset. So forget about any real-time debugging, as this requires additional 4 high-speed 1bit ports to implement xCONNECT link. But in my case I also have to reconfigure AK5572 ADC on every sample rate change. This means utilizing last two available ports for I2C bus and no additional pins for mandatory master clock select and codec reset.
Only viable solution to this problem is an I2C I/O port expander like a PCA9536. This in turn means quite an extensive modification of a reference design as “app_usb_aud_l1” which is meant for XS1 devices doesn’t even use I2C.
XMOS programing environment xTIMEcomposer is quite a mature software and I didn’t found it to be very difficult to get a hang on. XC programming language on the other hand – broke my brain many times again and again. I must admit – I’m not a programmer. I know some C from 8051 days, some Verilog for times when simple glue logic is not enough and some high level Python to make my life easer on linux. That’s more or less it (CCS, html doesn’t count….). So wrapping my head around this basic C with parallelization took some time. Whole reference design is a strange mix of C/C++, XC and assembly. I’m not kidding – inline assembly language in 2021! It looks like dev’s had to use these “hacks” in places were timing is absolutely critical.
I ended up adapting “app_usb_aud_l1” for a newer “lib_i2c” I2C library which uses whole different server/client approach to multitasking instead of endpoints. This was the only way I found to call I2C from audiostream and audiohw functions and not brake any core modules by doing so. Also implementing/debugging whole I2C config routines for different IC’s and correcting all compile errors took some time. Probably couple months have passed before I’ve got a working binary and documenting this process would require a separate article.
Power supplies
The decision to make this interface bus powered had a tremendous implications on the whole project. USB 2.0 standard allows for high-power devices to draw 500mA of current from the bus after they enumerated as such. In practice – not a lot of manufacturers are playing by the rules. This led to a current de-facto situation of allmost all USB2.0 hosts (notebooks, motherboards etc.) being capable of supplying about 1A without any problems. This current is limited only by a polifuse used for that port or whole USB hub. There are couple exceptions I know, for instance some apple products have implemented actual current measurement on USB port and are not happy with over-current situations.
USB side switching power supply’s.
I decided to play by the book (I also use macbook for in-field measurements) so a lot of care had to be taken with power budget limitations. This in turn means maximum efficiency and switch-mode power supply’s. As can be seen from above schematics – even 1V8 supply for USB chip which draws only 20mA is switch mode. This doesn’t effectively mean a lot of noise. As I’m always emphasizing – it’s all about implementation. Modern switch IC’s operating in Mhz region (way above sampling frequency) has current limiting and with a proper PCB layout/decoupling – excellent EMI profiles can be achieved. AP2151 is limiting inrush current, but as practice shows – could be omitted in the final production.
DC-DC isolated switching power supply’s.
Audio side isolated power supply’s are generated with SN6505 transformer driver IC’s. Choice was due to a really small footprint (always great for EMI) and readily available transformers from Würth. Also these parts have external clock input and can be synchronized to sample rate/master clock, thus totally eliminating any switching noise from sampled data. This is how they are working in this pre-production sample I build. Si5356 pll is configured at boot-up to divide incoming master clock to 768/704kHz so that SN6505 are switching synchronously at 384/352kHz (PCLK/2). Further extensive testing had shown that there are no measurable difference in noise floor spectrum when SN6505 are free-running or synchronized. This is all due to adequate PCB layout and internal SN6505 clock having build in spread-spectrum.
Analog power supply’s.
All analog sections have their dedicated linear regulators. DAC/ADC analog supply’s are regulated by NCP718 which will be replaced by newest and greatest low-noise from TI – TPS7A20. That is as soon as hunger games are over. Now they are gone same day as major distributors get them. At least popular 5, 3.3V versions in SOT-23 packages. Gone as the hot buns.
All op amps are fed with low-noise MIC5205/5271. These are more then adequate for the job (op-amps have already good PSRR). And finally the cherry on top – LT3042. These are Ultralow Noise, Ultrahigh PSRR (and Ultra-pricey) RF Linear Regulators from AD. They are the parts that almost solely define performance of AK4490 DAC. I have also used LT3042 to generate ref. voltage for ADC as I plan to make some long-term DC voltage measurements. There should be other cheaper alternatives with same voltage stability. ADC doesn’t seem to be that picky about it’s voltage reference impedance (more on that later).
LTSpice simulated LT3042 output impedance. 7mA load (upper trace) vs. no load.
LT3042 usage as voltage reference is nothing new. It has been done in several AK4490/93 DAC incarnations I have seen, but all these designs had overlooked one important detail about this part. In order for LT3042 to achieve a flat output impedance, up to the frequency where output cap starts to dominate, there must be a minimal load current present. But there is no DC component on VREF pins! Simulation above perfectly illustrates that. At these low-ish frequencies I don’t see any reason not to believe it. So a green LED on LT3042 output are just what a doctor prescribed. It also works as a “VREF_OK” indicator.
Choosing the right tools
Probably most important part in a successful ADC design is input driver implementation. In order to achieve project target SFDR it is essential to have a good grasp of what is going on there and how a modern Δ∑ ADC’s work. Again, this a very broad topic that I’m not gonna cover here. There are good primers like this training webinar from TI. I will however borrow couple slides and do a TL;DR.
Simplified input of a modern ADC.
All modern Δ∑ ADC’s use switched cap technique. This means that a switch S2 opens and switches S1 are closed at the beginning of sample time. Csample charges and S1 switches are disengaged. Modulator samples Csample and closes S2 to fully discharge it at the end of the sampling time. Cycle repeats at modulator frequency Fm. Cdiff provides charge reservoir for Csample and together with Rflt isolates driver and provides some anti-aliasing filtering.
Waveform at ADC input and FFT of a captured AC input.
Looking at the resulting ADC input waveform it becomes pretty obvious that a job of input driver IC is to ensure as short settling time as possible. Otherwise sampled voltage will be higher/lower then true input and distortion products will be generated in the sampled data. An amplifier with more gain bandwidth product will be able to provide the instantaneous current demanded by the ADC inputs more quickly. As a result, the input voltage will settle faster.
SFDR vs. Fm of different ADC input driver IC’s having various GBW product.
On the other hand, it can be said that lowering modulator frequency Fm also lowers the driver GBW requirements as now there will be more time for a signal to settle. Unfortunately AK5572 (as all other audio ADC’s I know) doesn’t allow user to choose modulator frequency.
Waveform of AK5572 ADC input (24.576Mhz master clock, SR in-depended).
A good rule of thumb is to choose a driver with GBW of 10-15 times the Fm. Above is my scope shot of AK5572 input and it seems that a modulator is running at 12.288Mhz or MCKL/2. This makes sense as this is also maximum frequency this ADC excepts in DSD mode. Following above logic a THS4551 fully differential amplifier with GBW of 135Mhz was chosen.
Driver for AK5572 ADC input (Fc=550Khz).
Anti-alias filter must have it’s pass band at half Nyquist frequency (Fs/2) so that out-of-band noise would not alias back and add to the noise floor of usable BW. In modern oversampling ADC this filtering is done in digital domain, but signals at Fm±Fs (12.288MHz ±Fs for AK5572) can still fold back. A nested feedback anti-aliasing filter network was designed around THS4551 that provides -80dB attenuation at 12.288MHz Fm and effectively prevents any fold-backs.
Another very important thing to mention here is the fact that all of the above applies to ADC/DAC VREF input as well. It is a less know fact that internal circuitry is absolutely the same switched capacitor type! Sometimes it is internally buffered like (I guess) in AK5572 and thus not requiring much attention to surrounding circuitry. But sometimes it’s NOT, like (I guess) in AK4490. Then VREF input should be treated with same care as an analog one. After all – sampled/generated data is as good as the reference it’s compared with.
Driver for AK4490 VREF input (evaluation board).
This is the reason why AK4490 evaluation board uses 50MHz GBW AD817 series regulator and why only high BW regulator like LT3042 are up to the job. I suspect something along those lines would be even better and it’s something to try in next revision.
Analog front-end
There is still some signal conditioning to be done, before we can feed voltage to/from ADC/DAC. This involves some buffering and voltage level adjustments. Here the THD/noise performance of op-amps should be selected appropriately as to not compromise system performance.
Data-table for a currently produced low-thd op-amps.
Any other time I would just throw a bunch of LM4562 together and call it a day. This time however there is a hard constrains to work with. First and furthermost there is a strict power budget. So a 10mA quiescent current per op-amp is out of the question. Also power rails are limited to ±5V as going any higher means more current demand from primary side and less efficient DC-DC conversion.
Then there is need for high input impedance to the ADC. I chose 1MΩ because I often measure high impedance circuits where any additional loading on the nodes invalidate the measurement results. This means that op-amp has to have a very low input current as every nA will produce 1mV of offset at op-amp output.
Input buffering and SE-to-BAL conversion for ADC.
This have effectively limited op-amp selection to a JFET input OPA164X series. These are wonderful parts having spectacular 2pA of input current and able to do 4-digit distortion specs with just a 1.8mA of quiescent current. However, there is no free lunch. Ever. Especially in electronics. And the price to pay here is a limited input swing to the positive power rail (Vpos-3.5). This in turn means that using 5V rails ADC input swing is limited to ~1.8Vrms before there is a sharp raise in distortion.
In my case this is an acceptable compromise to make. If a full 2Vrms input swing is required and 100kΩ input impedance is sufficient, then op-amps can be changed to OPA1612 without any performance penalties.
ADC op-amp input protection & attenuation.
Having fried enough of measurement equipment inputs over my hobby career I felt like proper protection circuit would be a very welcome addition here. Input attenuation is made using simple MELF resistor divider and rotary switch. So -20dB and -40dB input positions are already current limited by resistor divider. 0dB input current is limited to 1mA using back-to-back connected LND150 depletion mosfets. Input voltage is limited to about ±5V using 4V3 zeners and 1N4148 diodes. This adds 4pF to a total input capacitance and limits the upper frequency BW when using -20dB and -40dB input positions.
DAC output filter and differential driver.
On the DAC side of things, there is nothing special going on. Output filter is designed using THS4561 FDA op-amp for a passband of 170KHz and Fc of 530kHz at -3dB. Pass-band is chosen as maximum usable AK4490 output frequency. Even though this DAC is capable of 768kHz sampling rate I will be running it up to 386kHz and digital filter roll-off will kick in much sooner then that (see datasheet).
Second THS4561 is used only as a balanced output driver. First stage is already loaded with 1kΩ BAL-to-SE converter. So driving another 600Ω of output load in parallel and still meeting THD specs is very unlikely.
PCB design and system integration
Packing this whole shebang into a reasonable size box (150X105X55 mm) has proved to be challenge on it’s own. I have a pretty OK spatial thinking/orientation but I would not go for a blind attempt in a project like this. So I have designed a PCB with a real-size 3D models of all parts and then checked how everything fits together in a 3D modeling package.
3D rendered image of main PCB.
Software I used was KiCad v5.1.9. As any other PCB design software – it has it’s quirks. But if you know were to put the pillow – it’s not that bad. Also, if you put the price (which is free) into perspective – then it becomes a really attractive open-source alternative to Altium and such. It comes with a 3D integration as standard at I’m convinced that this is a way to do things in 2021. Main PCB is a 4-layer job as component density is quite high. Front panel PCB’s are 2-layers.
3D rendered image of all assembly in FreeCAD.
KiCad doesn’t allow multi-pcb projects, so final assembly has to be done in other CAD software. Fortunately there is also an open-source alternative for a CAD like Solidworks – FreeCad. PCB’s can be exported as STEP files from KiCad ant imported to FreeCad. This software is still in an early version of 0.18, so doing something more then just positioning elements and checking tolerances is a major pain. I spend some 3-4 hours to just draw this simple 2 part aluminum box. It’s a 5 minute job in Solidworks.
3D rendered image with raytracing of all assembly.
It also doesn’t come with ray-tracing so to produce such a photo-realistic images third party tools must be used. Not critical for development but marketing department wouldn’t be happy at all ;).
Final Assembly
I ordered PCB’s from JLPCB. And although they don’t pay me anything I will say I had a very pleasant experience. When it comes to price – it’s unbeatable. 20€ + shipping for 5pcs 100×100 4-layer PCB + 2 stencils is insane!
Quality is also really good. It’s not up there with reputable European manufacturers, but c’mon! For the 1/10th of the price those PCB houses ask – I’ll take it, thank you very much.
JLPCB 4-layer standard PCB, 0.5mm IC pad pitch.
Next on the menu was PCB assembly. This main board has ~500 elements and it’s a two side job. Soldering 500 elements by hand with just a soldering iron and hot-air gun is something I will leave for my retirement days.
Here I used stencil to transfer soldering paste on to the PCB. Then I fastened PCB in my BGA rework station and I have become a human pick&place machine for I don’t know… two days maybe? That’s for both sides. It’s not as bad as it sounds. I actually find this process very meditative. Wouldn’t want to repeat often though. Soldering was done with bottom heaters set to 200C and with a Quick 861DW hot air station.
After this exercise, soldering simple 2-layer front panel PCB’s was a walk in a park. This assembly has a total of 4 PCB’s. It could be simplified down to 3, but I couldn’t find any suitable 90° push-button switches.
Lastly there was some machining to be done. Front panel needs various holes for connectors and knobs. Also it helps to know what all of those connectors and knobs are there for. If you think I must remember what goes where because I designed it – think again :).
All operations were done using my home-brew repurposed 3D printer running Marlin 2.0 firmware and driven directly by a LaserWeb software. Not the most high-end CNC setup, but does the job. Engraving letters with a 0.2mm drill bit on this un-machinable clay like chinnesium (which suppose to be aluminum) is a really fun exercise! (Not.)
ADC performance evaluation
All theoretical considerations and various simulations are a good tools to minimize development time and board re-spins. But as the saying goes – the proof is in the pudding. When all is said and done, boards are assembled and tested, it’s time to actually measure the darn thing. As we expect distortion products to be at a ridiculous levels of -120dB or below, measuring gear and setup needs to be metrological-grade.
Victor’s reference oscillator feeding MI-1 measurement interface.
Unfortunately I have no access to AP measurement gear, which would be a industry-standard solution for evaluating a piece of kit like this. So I had to be creative and above is the result. Box with a fancy name of “Ultra Low Distortion Reference Oscillator” contains a well known and many times reproduced “Victor’s oscillator”. Two versions were build for 1kHz and 10kHz reference sine-wave signals. Having expected distortion products below -160dB and -140dB respectively, this should be adequate tool for ADC performance evaluation.
Spectrum of a 1kHz reference signal at -1dBFS (48kHz sample rate, 65k FFT, Hanning window).
This time I used REW software. It’s my default tool for acoustic measurements, but over a last couple of years it’s “Real Time Analyzer” got a lot better. Now I feel like this has become a mature tool for a spectral THD evaluation. It doesn’t do overlays, so there is no way to make L-R channels show together in RTA window with all the fancy statistics. So I had to make a GIF animation. After some ADC driver circuit fine tuning – above is a result. All harmonic and non-harmonic products are well below -120dB on both channels at -1dBFS input level. Going any higher results in a sharp THD rise as is the case with most modern ADC’s (they all spec. at -1dBFS).
Couple words about measured THD+N numbers. There is quite some discrepancy on how particular software is calculating these numbers. I suspect there is a lot at play here, but it’s not just max available FFT size to capture all spurious information (REW shows the same THD+N numbers from the point when a reasonable sample-rate/FFT-size ratio is reached). My guess is that different software has different algorithms for “in-bin” power detector. It’s probably done as peak-to-peak detector in REW, and for noise we want a simple average. I’m not talking here about “sample averaging”, it’s about how that sample is transformed in the first place.
Spectrum of a 1kHz reference signal at -1dBFS (ARTA, 48kHz sample rate, 131k FFT, Hanning window).
To better illustrate my point – above is a spectrum captured with ARTA software. Spectral content looks exactly the same, but calculated THD+N numbers are equal to -108.8dB and -108.6dB for left and right channels.
Spectrum of a 1kHz reference signal at -1dBFS (SpectraPLUS, 48kHz sample rate, 131k FFT, Hanning window).
And here is my most beloved SpectraPLUS. Calculated THD+N (or SINAD) results are -113.9dB and -113.2dB respectively. That’s a couple dB better then datasheet spec. of -112dB. Here, all settings being the same, much “lighter” noise-floor spectrum is clearly visible with a naked eye. Hence my previous assumption regarding different detector algorithms. I now wonder how it’s done in AP software? After all this where datasheet numbers come from.
It also should be noted, that input sensitivity is only 1Vrms for 0dBFS. This is limited by input op-amps. So going for 2Vrms (standard for most sound cards) would bring reference oscillator noise floor 6dB down and improve THD+N numbers even further.
Spectrum of a noise-floor (Inputs shorted, REW at 352kHz sample rate, 1M FFT, Hanning window).
Noise floor can be pushed down to -160dB or even further using large FFT sizes. Not a bad result for all-switch-mode-bus-powered device! Really clean spectrum with no leakage contamination. Sharp noise rise from 20kHz is expected here as this is how all modern Δ∑ converters reach these impressive in-band noise performance – by shifting quantization noise out-of-band. Not a very creative approach as this renders all modern audio ADC’s incapable of low noise measurements above 20kHz. One exception was AK5397 used in RTX6001 analyzer, but it’s long since EOL.
Spectrum of a 1kHz reference signal at -3dBFS ( SpectrPLUS 48kHz SR, 131k FFT, Hanning window).
Lowering input level to -3dBFS pushes all harmonics down to -130dB and brings us in to the mythical region of 4-digit-distortion. That’s when a full audio nirvana can be reached and prerecorded virgin muses start to emerge from your speakers! But since other channel is still in a 3-digit-zone I’m not sure this will work in my case. Muses might be not-so-virgin after-all or something else could go wrong… 🙂
Spectrum of a 1kHz reference signal at -1dBFS (REW 48-384kHz sample rate, 65k FFT, Hanning window).
Sample rate has absolutely no influence on spectral content. And this makes sense as I measured internal modulator always running at a fixed 12.228MHz. So in a sense this ADC is always sampling at max SR and requested SR is just adjusting data transfer rate.
Going from balanced to single ended is almost not visible at all. It adds a dB or so to THD but that’s about it. No point to even publish it here.
Spectrum of a 10kHz reference signal at -1dBFS (BAL input, SpectraPLUS 192kHz sample rate, 131k FFT, Hanning window).
What does change things a bit is increasing reference frequency to 10kHz. There is a noticeable increase in THD and 3rd harmonic jumps to -108dB or so. Enough of these static measurements, let’s see how our inputs are doing when frequency is varied.
Spectrum of a 10kHz reference signal at -1dBFS (BAL input, SpectraPLUS 192kHz sample rate, 131k FFT, Hanning window).
This is a loop-back THD+N sweep over frequency. Although it includes DAC THD+N component too, clear trend can be seen. Distortion starts to slowly increase at 7kHz or so. This implies that THS4551 is working “at the edge” and there is still some improvement to be made by going for a much higher BW THS4541. Also OPA1641 influence should be considered as it is working way below datasheet ±18V supply values.
Input frequency response with 0dB attenuation (ext. generator, SE input, REW 384kHz sample rate, peak-hold trace).
Let’s see how inputs are doing BW wise. Above is a measured frequency response of a whole ADC input chain. Input is driven by external Rigol DG1022 20MHz signal generator in a sweep mode. Digital filter is set to default short-delay sharp-roll-off. With a 384kHz sample rate digital filter -3dB corner is at around 124kHz. I suspect this will not improve much even at max 768kHz SR.
Input frequency response with different attenuation (Loop-back, REW 384kHz sample rate).
And finally this is a frequency response using different input attenuation values. At first this might look perfectly fine, but more curious reader would notice that a biggest attenuation produces a flattest response. This doesn’t make much sense and got me head scratching a bit. At -40dB attenuation we have 1MΩ|10kΩ resistor divider. Everything beyond that is driven by a high 1MΩ impedance up to the op amp pin. So this could be a mix of a board parasytics reacting with complex op-amp input impedance. It doesn’t take much to boost a 1MΩ line couple dB’s. In practise this is more of a feature then a bug. After all, proper interface calibration file should be loaded before making frq. response measurements anyway.
DAC performance evaluation
Measuring DAC distortion has it’s set of the problems. As we already verified excellent ADC numbers it would be tempting to just do a loop-back test and measure DAC harmonics. But there is a catch. When both chips are running in a same synchronized master clock domain, generated DAC distortion harmonics can easily add/subtract with inherent ADC ones thus invalidating measurement results. This is because both systems distortion products are essentially phase-locked by a system master clock.
Spectrum of ESI Juli@ ADC 1kHz reference signal at -6dBFS (REW 48kHz sample rate, 65k FFT, Hanning window).
Much better solution is to use other ADC that is running asynchronously. For that purpose I fired up my ESI Juli@ sound card and tested it’s ADC performance. Above is a spectrum of 1kHz reference signal which would suggest that we have an SFDR of -128dB at -6dBFS input. This should be just enough to not hide any DAC harmonics at expected -110dB or so. Of course any THD+N numbers with this setup will be meaningless as much higher dynamic range (lower noise-floor) are required to measure them accurately.
Spectrum of DAC generated 1kHz signal at -1dBFS (Juli@ BAL input, REW 96kHz SR, 65k FFT, Hanning window).
Looks like one channel is comfortably within 120dB SFDR and other got 2nd harmonic peeking 3dB higher at -117dB. That’s a 10dB improvement over expected 110dB SFDR from evaluation design! I suppose I could get other channel down to -120dB also by fiddling around with filter components and Vref input. But at this point it becomes more academic then anything of a real value. Again, sample rate has no influence on the spectrum.
Spectrum of 1kHz system loop-back signal at -1dBFS (BAL input, SpectaPLUS 96kHz SR, 65k FFT, Hanning window).
And finally here is how I will be using this interface 90% of the time. By injecting DAC generated signal in to DUT and measuring resulting spectrum. At -6dBFS ADC input level 120dB SINAD can be reached on a better channel! Again, not a bad result for a bus powered and high input impedance compromised device.
Specs and schematics
I don’t like emphasizing numbers. It’s so easy to manipulate them that it becomes a highly speculative topic without a rigorous 3rd party verification. So below are just a couple ones that I’m quite confident with.
- 386/352kHz maximum sample rate, 2ch in / 2ch out
- 120dB spurious free dynamic range for both ADC and DAC (1Khz signal at -1dBFS)
- -107dB or better THD+N for ADC (1Khz signal at -1dBFS)
- 124kHz ADC bandwidth (-3dB, 386kHz sample rate)
- 90kHz loop-back bandwidth (-3dB, 386kHz sample rate)
- 0dB, -20dB, -40dB input attenuation
- Internal loop-back switch for using channel as a timing reference
- 1MΩ input impedance
- Analog output: 2Vrms@0dBFS (+6dBV, +8.2dBu) Balanced/Single-ended, DC/AC coupling
- Analog input: 1Vrms@0dBFS (+0dBV, +2.2dBu) Balanced/Single-ended, DC/AC coupling
- Max 400VDC (160VAC) input voltage (AC coupling)
- 500Vpp capable 0dB input current-limiting (DC coupling)
- ESD output protection
- 2.5kVAC galvanic isolation from USB side
Current consumption from USB port at “Idle” and “Active” states.
Below are the latest schematics for download with all small bugs of a first V1.0 prototype board corrected.
