TDA1541(A) Digital Input Attenuation

First pieces of information regarding the subject started floating around internet by early 2003. I can’t remember exactly where I found it and I don’t think I understood what was meant by the OP at that time, but since I was already doing a lot of research about digital-to-analog converters, I made a note to my self.

TDA154x digital inputs are PNP differential stages, the reference voltage made by two forward biased diodes.

–Henk ten Pierick, circa 2003

I didn’t gave this a second thought until years later, when I started playing with different TDA154x based CD players. Then I started looking for every trick in my book to extract more potential from those chips and stumbled upon the quote above.

Now I, as every other sane person should, don’t believe everything I read in internet. Otherwise I would be dead or seriously handicapped long time ago. So a quick google search was in order and it looks like Mr. Henk was really active and knowledgeable poster on time-nuts mailing list and many audio resources. Also it’s mentioned as a colleague by Guido Tent and Jan Didden, publisher of Linear audio. So OP’s personal credibility leaves nothing to be doubted about, and it’s alleged personal connections inside Phillips laboratories makes him a valuable information resource. Unfortunately he passed away in 2013.

TDA1543 input pins BCK, WS and DATA (Phillips datasheet).

There is also a good hint in TDA1543 datasheet called “Circuits at the input and output pins”. At first look it doesn’t reassemble PNP differential stage, but that’s because it’s an conceptual schematic. However from our outside perspective it should behave exactly the same.

TDA154X digital input pins internal schematics (suggested)

It’s hard to know for sure, but probably this is how input looks like schematically. PNP differential stage forming a most primitive voltage comparator. On real IC die it might have all kind of “bells and whistles” like Darlington pairs and additional cascoding, but it wont change the essence.

If all the above presumptions are correct, this has several far reaching implications:

  • All digital input bandwidth should be limited to 10MHz
  • Voltage swing on all digital inputs should be limited to 400mV
  • All attenuation circuit elements and their values should be chosen such, that would not compromise timing uncertainty
Standard, junction- isolated bipolar IC proccess

To understand the reasoning behind the statements above, lets look how bipolar process for IC manufacturing works. The substrate is P type crystal silicon in which n-epitaxial layer of transistor base is contained. On top of that, two parallel P-regions are formed which make the emitter and collector. From the picture above, it should be pretty evident that all the input capacitance is base-to-substrate. Fast input signal will induce capacitive currents which will find their way to sensitive analog circuits on the same IC substrate.

Also substrate shouldn’t be thought as a “black hole” where those currents will just disappear. They will return to the digital source through analog and digital ground pins. Because impedance of those pins are not zero, those currents will induce voltage. This voltage has a technical term of “ground bounce” and it will add directly to analog output.

TDA1541A analog output with BCK induced interference

It’s really easy to check it for your self. Just look at any TDA1541 output with scope having enough bandwidth and witness spikes from incoming bit-clock. Now imagine how this trace becomes filled with “digital fur” from all the changing data and all of that rides on top of audio signal. This will massively upset any op-amp based IV stage and will add to already small output compliance budget.

TDA1541A digital inputs datasheet rise times

Given that usual gain bandwidth of PNP transistor, made by lateral process on integrated circuits is below 10MHz, it now becomes more evident why TDA1541 datasheet states maximum rise times of 32ns. Which by no coincidence calculates to ~10MHz (BW=0.35/0.032ms). Everything faster than that has no influence on internal comparator triggering uncertainty and will just produce more garbage at output.

Another angle of attack to the problem is voltage swing. More voltage – more current goes through parasitic capacitance and into substrate. But what is the absolute minimum for reliable data latching operation?

TDA1541A digital inputs datasheet logic levels

Datasheet says 1.2V between HIGH and LOW, but notice how unconventionally max specifications are written! They are in current, rather then usual TTL voltage levels. This is a dead giveaway for current-steering logic inputs. So we can do better than this. We just have to know exactly where the bias point is and we can figure it out by measuring volt-ampere characteristic of an input pin.

TDA1541A digital input volt-ampere characteristic at 25C

From the graph above, we see that a mid-point is around 1.3V. This is where both differential pair transistors are at equilibrium ant state change happens. Whole switching range is very narrow between 1.2V and 1.4V, so only 200mVpp is needed to trigger the inputs. This value will drift a little with a chip temperature, so 400mVpp should be a reasonable safety margin. Now we have all the information needed to design a input attenuation circuit.

Input attenuator schematics for TDA154x DAC’s

And it doesn’t need to get any more complicated than above (although it certainly can). Here two 1N4148 diodes mimic internal reference voltage and provides around 1.3V bias voltage. Back-to-back connected 1N5711 diodes limits voltage swing to around 400mVpp and 1uF film cap keeps bias voltage stable. Input RC circuit does the rise-time (BW) limiting and it’s values should be selected depending on incoming signal. Needless to say, that every signal (BCK, LE, DATA_L,DATA_R) needs it’s own attenuator.

For usual CD players, where 5V TTL signals are present at X4 oversampling (5.6MHz bit-clock), 1k and 100pf works well and limits rise time to around target 32ns. However TDA1541A works fine up to 384k sample rate and 12.2MHz bit-clock in simultaneous data mode. Then you are probably using 3.3V level signals, so input RC values should be lowered to 680Ω and 47pF to reach the same rise times.

BCK (Blue) and DATA (Red) signals after attenuators

Above is a scope shot with resulting waveform of 6.1MHz bit clock and data signals after attenuation. Voltage swing is about 500mVpp and rise time of 37ns. This is with oscilloscope probe load of 10pf so normally it’s less than 30ns. Data “eye-width” is totally fine and all samples are latched successfully. It’s pretty obvious that increasing frequency twice (to 384k sample rate) will unacceptably degrade eye diagram, so input resistor should be lowered to 680Ω.

BCK (Red) and analog output (Blue) signals after installing attenuators

On analog output pin, we went from 55mVpp spikes to almost no visible modulation at lowest 1mV/DIV scope range (100MHz BW). This proves the undeniable effectiveness of the measures applied. However, as soon as you start introducing any elements in digital signal path, people start screaming words “jitter”, “fluctuations” and finally when all else fails – “quantum”. This is quite understandable as there is so much BS floating around this subject, which makes it a hot pile of speculation. Let’s shed some light here and see how much jitter we actually generated with attenuator. Warning, some napkin math ahead.

Looking into schematics above, we see only one passive element in signal path – resistor. Both diodes are not conducting during signal transition and input capacitor is good enough to not exhibit any piezoelectric disturbances. Then resistor thermal noise is the only noise source in the system. We already determined that we limit our bandwidth to 10MHz with input RC, so any online calculator will tell you that 1k resistor noise over that bandwidth is ~12.7µV.

Amplitude noise to timing jitter conversion

Next let’s see what corresponding literature has to say about translation of Noise to Timing Jitter. There we find that using small-signal perturbation theory it can be shown that:


Or in plain English – timing jitter Δt is increasing with rising noise amplitude ΔA and decreasing with faster slope, or slew rate k. This is where usual wisdom of “faster signals reduce jitter” comes from. And it’s true in general sense, all else being equal. We already know noise amplitude and we can eyeball slew rate being ~60ns/V or 0.016V/ns from a scope shot above (30ns/550mV). This would calculate to timing jitter of:

Δt = 12.7/0.016 = 765 femto sec. or 0.7ps

To put this number in perspective, usual FPGA gate has 100ps of jitter. Hybrid micro-controllers like XMOS used for USB-to-I2S converters can have anything between 500ps and 2000ps of jitter before re-clocking, depending on actual implementation. A lot of CD players I have measured performs even worse than that. So 0.7ps is not zero additive jitter, but for all practical intents and purposes can be safely ignored.

Finally couple words about actual sound improvements. This will solely depend on what is further down the audio chain. Tube I/V conversion stage is not that sensitive to HF garbage, so difference is not so audible as with op-amp stage. But it’s still there and comes from the fact that less internal noise means better conversion time accuracy. Same thing can be said about other system elements. If no filtering is applied with tube I/V stage, and all HF garbage is faithfully reproduced down the chain – some transistor amplifiers could be upset. Then installing attenuators will be really audible. With tube amps, this difference will be not so obvious. And so it goes. Generally this is a really worthwhile “mod” to any TDA154X device and every single person who tried it reports positive experience. 

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