In the first part we took a look at the theoretical principals of DEM operation and found out some limitations of actual implementation. We saw how sensitive internal oscillator circuitry is to incoming digital signals and measured resulting linearity degradation. Alternative approach of lowering DEM frequency was suggested that will be the topic of this second part.

We have made a good theoretical hypothesis on how and why low frequency DEM clock makes sense. In order to find out if it’s even a viable solution that can be implemented with real world elements, some further research and testing are needed. If data analysis will look promising, in-situ experiments with TDA1541A chip will be performed to validate the presumption. Just like the best practice of scientific method asks.

Let’s begin by looking into TDA1541 analog output on-chip circuit (above) and see what could go wrong. Here I_bit is our bit-current and it is represented by current source to which a C_ext filtering capacitor is connected to. We know that current source connected to a load resistance manages the voltage in such a way as to keep the current constant. Also ideal capacitor voltage (charge) can’t change without current changing. Adding two together we see that this is a place where “real” current averaging of DEM circuit is taking place. Here we make our first conclusion:

It also means, that if we connected ideal capacitor having infinite capacitance and let it reach averaged voltage, DEM circuit could be stopped entirely! Unfortunately charging infinite capacitor means waiting for universe to end so let’s get back to reality. Here we have capacitors that (amongst other flaws) have leakage current I_leak. This current is now “stealing” our accurate bit-current and sending it to ground, before it reaches the output. If substantial enough, it could even upset all cascoding stages. This is unlikely though as load resistance is quite low (4-7kΩ).

To have a better picture of all the influence, let’s look at the full conceptual schematics. Here we see that 7 filtering capacitors are used for 6 most significant bits and one shared current for 10-bit passive divider. Now consider what happens if all leakage currents are equal? In that case, all 6 of MSB currents, together with the shared one, are offset by equal amount. In theory this doesn’t introduce any non-linearity, just a static offset error (not important in audio). Let’s make a note, that:

However a real circuit passive 10-bit divider will loose some of it’s accuracy as now it has smaller (62.5μA – I_leak) current to work with. Also it’s very unlikely that real capacitors would have exactly equal leakage current. Let’s call this difference between any two leakage currents ΔI_leak and say that now it’s the main source of non-linearity.  But how much of ΔI_leak is still acceptable?

TDA1541A datasheet states that guaranteed integrated and differential linearity error is 1LSB maximum. Great. But what does that mean? To answer this question, we have to define LSB and what differential and integral non-linearity errors are. Let’s quickly dive into this tech-term rabbit-hole.

To put it simply:

• LSB – or Last Significant Bit is minimum 1 step value that DAC can reproduce.
• Differential error is the maximum deviation between an actual step height and the ideal value of 1 LSB.
• Integrated error is maximum deviation between ideal transfer function and any real point.

Both of them are usually specified in relation to 1LSB. Difference between two are subtle and should be thought as either looking into minimal one-step DAC resolution error or how those step-errors can accumulate over whole output range.

It also should be noted, that relationship between these errors and harmonic distortion of a DAC is not simple. Using appropriate math it can be shown that:

So increase in noise floor will mean increased DNL and increase in THD will mean higher INL. This will come handy later when evaluating results by capturing large FFT size spectrum. Otherwise automated measurement system for generating sub-sets of input codes are needed to evaluated each bit-error with metrological grade precision.

Intuitively this relationship can be found by looking at a real transfer function. If it goes zigzagging around ideal axis with lot’s of small DNL errors, at output signal we will have lot’s of non-harmonically related distortions and they will add to the system noise floor. However symmetrically deviating transfer function will have distortion products with harmonic relationship. So for instance bow-shaped INL curve will produce 2nd harmonic distortion and with s-shaped one 3rd harmonic will dominate etc.

Now let’s suppose that average TDA1541A will have 0.75LSB DNL and INL errors. By introducing additional 0.25LSB error, we would still meet 1LSB datasheet specification for DNL.  Same thing is true for INL, but only if this additional 0.25LSB error has truly random distribution.

Summarizing all the above, it is safe to assume that acceptable value for ΔI_leak should be less than 0.25LSB. In absolute terms, that means a current of merely 15nA.

ΔI_leak < 0.25LSB (15.3nA)

This will be our target for DEM capacitor selection. Let’s quickly remind our selfs that we are talking about delta between two leakage currents and not a total current here. For film or (small) MLCC capacitors, this is not a challenge as these capacitors usually have a total leakage current somewhere in that range. However we are looking to shift DEM frequency at least 3 magnitudes of order down, from 100kHz to 100Hz or lower. This implies increasing filtering capacity from usual 1μF to at least 100μF or higher. While 100μF MLCC capacitors exists, their leakage currents are substantial. For example 100μF 10V TDK capacitor in 1206 package, has only 1MΩ insulation resistance. This means 7.5μA current at 7.5V for MSB filtering. Film capacitors traditionally have almost non-existent leakage, but package size for this much of capacitance presents a challenge. Designing a PCB around that would be a non-trivial task at all, also cheapest 14 film capacitors of that size means budget hole of 300€‎ or deeper.

This leaves electrolytic capacitors as only viable option here (at least at the time of writing this). At first glance this is a terrible idea. Historically electrolytic capacitors are notorious for their leakage current and are best avoided in leakage-sensitive applications. But times are changing and there has been substantial progress made in this field. Particularly special low-leakage KL series of capacitors made by Nichicon looked very promising and launched further investigation.

I_leak = f(V, t, T)

Quick primer on electrolytic capacitor leakage. It’s a function of temperature (T), applied voltage (V) and time (time).

As evident from graphs above, it decreases with time and increases with applied voltage and temperature. Typical steady state I_leak,op are specified in datasheets as product of capacitance, rated voltage and self-discharging constant:

I_leak,op = const. x C x V

For Nichicon KL series it’s specified as 0.002CV or 0.2 (µA), whichever is greater after 2min. of applied voltage at room temperature of 20C. This means 5µA leakage for a 100μF 25V capacitor . It’s still a lot! And why choose 25V capacitor with higher leakage if maximum voltage on DEM filtering is 7.5V?  It’s because leakage current drops significantly when applied voltage is below nominal. Usually, if applied voltage is 30% of nominal voltage, leakage-current drops to 10% of I_leak,op. Then it boils down to 50nA for a 100μF 25V capacitor at 7.5V. At least in theory. This is totally acceptable so a batch of 25V 100μF and 680μF KL series capacitors was bought for further evaluation.